void InitPll(Uint16 val)

{

   volatile Uint16 iVol;

   if (SysCtrlRegs.PLLCR.bit.DIV != val)

   {

      EALLOW;

      SysCtrlRegs.PLLCR.bit.DIV = val;    //CLKIN=30*10/2=150MHZ

      EDIS;

   // Optional: Wait for PLL to lock.

   // During this time the CPU will switch to OSCCLK/2 until the PLL is

   // stable.  Once the PLL is stable the CPU will switch to the new PLL value.

   //

   // This switch time is 131072 CLKIN cycles as of Rev C silicon.

   //

   // Code is not required to sit and wait for the PLL to lock.

   // However, if the code does anything that is timing critical,

   // and requires the correct clock be locked, then it is best to

   // wait until this switching has completed.

   // If this function is run from waitstated memory, then the loop count can

   // be reduced as long as the minimum switch time is still met.

   // iVol is volatile so the compiler will not optimize this loop out

   //

   // The watchdog should be disabled before this loop, or fed within

   // the loop.

      DisableDog();

   // Wait lock cycles.

   // Note,  This loop is tuned to 0-waitstate RAM memory.  If this

   // function is run from wait-stated memory such as Flash or XINTF,

   // then the number of times through the loop can be reduced

   // accordingly.

      for(iVol= 0; iVol< ( (131072/2)/12 ); iVol++)

      {

      }

   }

}

转自《C2000手册》