We are in the final stage of writing our never-ending paper. Then, I "discovered" a bug in the code (numerical model for ecosystem). I was soooo upset. Eliminated all the snacks I could find in my office, including part of my lunch. Painfully corrected a subroutine; checked, checked, and checked again. TGIF!
The Cyclone III M9K embedded memory blocks may exhibit bit error in which the read bit is a 1 when the expected bit is a 0. The problem is caused by bitline coupling in the read output. The issue is rare and requires the presence of multiple conditions for the M9K block to be susceptible to the bit error. The conditions include the use model of the M9K block, the application data pattern, and the operating conditions.Designs using the M9K blocks in dual clock and widest data width (x32 or x36) modes are most susceptible to the bit error. Designs using the M9K blocks in single clock or narrower data width modes are not affected when operating within data sheet specifications. The problem is highly data-pattern dependent and triggered by specific data bit combinations. Lastly, the problem can be exacerbated by lower temperature and lower voltage operations. The presence of all these conditions does not imply a bit error would necessarily occur. In addition, if some or all of the conditions are not present, the error will not occur.
标签: bug
